cxl

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Versions in this module

v1

v1.3.2

Apr 15, 2024

v1.3.1

Apr 15, 2024

v1.3.0

Feb 5, 2024

Changes in this version

+ const CDAT_DSEMTS_Struct_Handle

+ const CDAT_DSIS_Struct_Handle

+ const CDAT_DSLBIS_Struct_Handle

+ const CDAT_DSMAS_Struct_Handle

+ const CDAT_DSMSCIS_Struct_Handle

+ const CDAT_SSLBIS_Struct_Handle

+ const CXL_DOE_PROTOCOL_TABLE_ACCESS

+ const DOE_PCIE_ext_cap_ID

+ const MB_CHECK_INTERVAL

+ const MB_READ_INTERVAL

+ const MB_WRITE_INTERVAL

+ var DOE_CAPABILITIES_Interrupt_Message_Number = u32field

+ var DOE_CAPABILITIES_Interrupt_Support = u32field

+ var DOE_CONTROL_Abort = u32field

+ var DOE_CONTROL_Go = u32field

+ var DOE_CONTROL_Interrupt_Enable = u32field

+ var DOE_STATUS_Busy = u32field

+ var DOE_STATUS_Interrupt_Error = u32field

+ var DOE_STATUS_Interrupt_Status = u32field

+ var DOE_STATUS_Object_Ready = u32field

+ var DSLBIS_data_string = [...]string

+ func CDAT_SSLBIS(entryCnt uint) cdat_sslbis

+ func CDAT_read_Entry_Request(entryHandle uint32) uint32

+ func DOE_DATA_OBJECT(DW_L uint) doe_data_object

+ type CDAT_DSEMTS struct

+ DPA_Length uint64

+ DPA_Offset uint64

+ EFI_Memory_Type_and_Attribute uint8

+ Handle uint8

+ Length uint16

+ Reserved uint8

+ Reserved2 uint16

+ Type uint8

+ type CDAT_DSIS struct

+ Flags uint8

+ Handle uint8

+ Length uint16

+ Reserved uint8

+ Reserved2 uint16

+ Type uint8

+ type CDAT_DSLBIS struct

+ Data_Type uint8

+ Entry [3]uint16

+ Entry_Base_Unit uint64

+ Flags uint8

+ Handle uint8

+ Length uint16

+ Reserved uint8

+ Reserved2 uint8

+ Reserved3 uint16

+ Type uint8

+ type CDAT_DSMAS struct

+ DPA_Base uint64

+ DPA_Length uint64

+ DSMADHandle uint8

+ Flags uint8

+ Length uint16

+ Reserved uint8

+ Reserved2 uint16

+ Type uint8

+ type CDAT_DSMSCIS struct

+ Cache_Attributes uint32

+ Handle uint8

+ Length uint16

+ Memory_Side_Cache_Size uint64

+ Reserved uint8

+ Reserved2 [3]uint8

+ Type uint8

+ type CDAT_SSLBE struct

+ Latency_or_Bandwidth uint16

+ Port_X_ID uint16

+ Port_Y_ID uint16

+ Reserved uint16

+ type CDAT_header struct

+ EntryHandle uint16

+ TableEntry []uint8

+ Table_Access_Response uint8

+ Table_Type uint8

+ func CDAT_read_Entry_Response(entryCnt uint) CDAT_header

type CXLMailbox

+ func (mb *CXLMailbox) SendMailboxCCIbyOPCODE(opcode uint64, args ...interface{}) interface{}

+ type Coherent_Device_Attribute_Table_Header struct

+ Checksum uint8

+ Length uint32

+ Reserved [6]uint8

+ Revision uint8

+ Sequence uint32

type CxlDev

+ Cdat *DOE_CAP

+ func (c *CxlDev) CDAT_init()

+ func (c *CxlDev) MeasureBandwidth() (float64, error)

+ func (c *CxlDev) MeasureLatency() (uint64, error)

type CxlMemAttr

+ AccessBandwidthMBs uint64

+ AccessLatencyPs uint64

+ ReadBandwidthMBs uint64

+ ReadLatencyPs uint64

+ WriteBandwidthMBs uint64

+ WriteLatencyPs uint64

+ type DOE_CAP struct

+ CDAT_valid bool

+ func (cdat *DOE_CAP) Get_CDAT_DSLBIS_performance() CxlMemAttr

+ func (cdat *DOE_CAP) PrintAllCDAT()

+ type DOE_Discovery_Response struct

+ Data_Object_Protocol uint8

+ Next_Index uint8

+ Vendor_Id uint16

+ type PCIE_DOE_EXT_CAP struct

+ DOE_Capabilities uint32

+ DOE_Control uint32

+ DOE_Read_Data_Mailbox uint32

+ DOE_Status uint32

+ DOE_Write_Data_Mailbox uint32

+ PCIE_ext_cap_hdr uint32

+ type PCIE_DOE_HEADER1 struct

+ DO_type uint8

+ Reserved uint8

+ Vendor_ID uint16

+ type PCIE_DOE_HEADER2 struct

+ Length bitfield_18b

+ Reserved bitfield_14b

v1.2.0

Oct 5, 2023

Changes in this version

+ const ACPI_CEDT_CXL_FIXED_MEMORY_WINDOW

+ const ACPI_CEDT_CXL_HOST_BRIDGE

+ const ACPI_CEDT_CXL_XOR_INTERLEAVE_MATH

+ const ACPI_CEDT_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRCUT

+ const CXL_CMPREG_BI_DECODER_CAP

+ const CXL_CMPREG_BI_ROUTE_TABLE_CAP

+ const CXL_CMPREG_CACEHMEM_EXT_CAP

+ const CXL_CMPREG_CACHE_ID_DECODER_CAP

+ const CXL_CMPREG_CACHE_ID_ROUTE_TABLE_CAP

+ const CXL_CMPREG_CAP

+ const CXL_CMPREG_EXT_HDM_DECODER_CAP

+ const CXL_CMPREG_EXT_SECURE_CAP

+ const CXL_CMPREG_HDM_DECODER_CAP

+ const CXL_CMPREG_IDE_CAP

+ const CXL_CMPREG_LINK_CAP

+ const CXL_CMPREG_NULL

+ const CXL_CMPREG_RAS_CAP

+ const CXL_CMPREG_SECURE_CAP

+ const CXL_CMPREG_SNOOP_FLT_CAP

+ const CXL_CMPREG_TIMEOUT_N_ISOLATION_CAP

+ const CXL_MEMDEV_MEMDEV_STATUS

+ const CXL_MEMDEV_PRIMARY_MAILBOX

+ const CXL_MEMDEV_SECONDARY_MAILBOX

+ const CXL_MEMDEV_STATUS

+ const DBG_LVL_BASIC

+ const DBG_LVL_DEEP_DETAIL

+ const DBG_LVL_DEFAUILT

+ const DBG_LVL_DETAIL

+ const DBG_LVL_INFO

+ const MB_DOORBELL_CHECK_INTERVAL

+ const MB_DOORBELL_TIMEOUT

+ var BACKGROUND_COMMAND_STATUS_REGISTER_COMMAND_OPCODE = u64field

+ var BACKGROUND_COMMAND_STATUS_REGISTER_PERCENTAGE_COMPLETE = u64field

+ var BACKGROUND_COMMAND_STATUS_REGISTER_RETURN_CODE = u64field

+ var BACKGROUND_COMMAND_STATUS_REGISTER_VENDOR_SPECIFIC_EXTENDED_STATUS = u64field

+ var MAILBOX_CAPABILITIES_REGISTER_BACKGROUND_COMMAND_COMPLETE_INTERRUPT_CAPABLE = u32field

+ var MAILBOX_CAPABILITIES_REGISTER_INTERRUPT_MESSAGE_NUMBER = u32field

+ var MAILBOX_CAPABILITIES_REGISTER_MAILBOX_READY_TIME = u32field

+ var MAILBOX_CAPABILITIES_REGISTER_MB_DOORBELL_INTERRUPT_CAPABLE = u32field

+ var MAILBOX_CAPABILITIES_REGISTER_PAYLOAD_SIZE = u32field

+ var MAILBOX_CAPABILITIES_REGISTER_TYPE = u32field

+ var MAILBOX_COMMAND_REGISTER_COMMAND_OPCODE = u64field

+ var MAILBOX_COMMAND_REGISTER_PAYLOAD_LENGTH = u64field

+ var MAILBOX_CONTROL_REGISTER_BACKGROUND_COMMAND_COMPLETE_INTERRUPT = u32field

+ var MAILBOX_CONTROL_REGISTER_DOORBELL = u32field

+ var MAILBOX_CONTROL_REGISTER_DOORBELL_INTERRUPT = u32field

+ var MAILBOX_STATUS_REGISTER_BACKGROUND_OPERATION = u64field

+ var MAILBOX_STATUS_REGISTER_RETURN_CODE = u64field

+ var MAILBOX_STATUS_REGISTER_VENDOR_SPECIFIC_EXTENDED_STATUS = u64field

+ func CEDT_CXL_FIXED_MEMORY_WINDOW(Record_Length uint) cedt_cxl_fixed_memory_window_struct

+ func CEDT_CXL_XOR_INTERLEAVE_MATH(Record_Length uint) cedt_cxl_xor_interleave_math_struct

+ func CMPREG_HDM_DECODER_CAP(Size uint) cmpreg_hdm_decoder_cap_struct

+ func StructSize(s any) int

type ACPI

+ func (a *ACPI) CedtHeaderSize() int

+ func (a *ACPI) GetCedtHeader() *ACPI_HEADER

+ func (a *ACPI) GetCedtSubtableSize(ofs int) int

+ type CEDT_CXL_HOST_BRIDGE struct

+ Base uint64

+ CXL_Version uint32

+ Length uint64

+ Record_Length uint16

+ Reserved byte

+ Reserved2 uint32

+ Type byte

+ UID uint32

+ type CEDT_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRCUT struct

+ Base_Address uint64

+ Protocol_Type byte

+ RCEC_BDF uint16

+ RCEC_Segment_Number uint16

+ Record_Length uint16

+ Reserved byte

+ Type byte

+ type CMPREG_LINK_CAP struct

+ CXL_Link_Ack_Timer_Control_Register uint32

+ CXL_Link_Control_and_Status_Register uint32

+ CXL_Link_Defeature_Register uint32

+ CXL_Link_Layer_Capability_Register uint32

+ CXL_Link_Rx_Credit_Control_Register uint32

+ CXL_Link_Rx_Credit_Return_Status_Register uint32

+ CXL_Link_Tx_Credit_Status_Register uint32

+ type CMPREG_RAS_CAP struct

+ Correctable_Error_Mask_Register uint32

+ Correctable_Error_Status_Register uint32

+ Error_Capability_and_Control_Register uint32

+ Header_Log_Registers uint32

+ Uncorrectable_Error_Mask_Register uint32

+ Uncorrectable_Error_Severity_Register uint32

+ Uncorrectable_Error_Status_Register uint32

+ type COMPONENT_CAPABILITIES_HEADER struct

+ Capability_ID uint16

+ Capability_Pointer bitfield_12b

+ Capability_Version bitfield_4b

+ type COMPONENT_REG_HEADER struct

+ Array_Size uint8

+ Cache_Mem_Version bitfield_4b

+ Capability_ID uint16

+ Capability_Version bitfield_4b

+ type CXLMailbox struct

+ func (mb *CXLMailbox) Mailbox_cmd(opcode uint16, payload []byte) (uint16, []byte)

+ func (mb *CXLMailbox) Mailbox_cmd_clear_event_records(event uint8) uint16

+ func (mb *CXLMailbox) Mailbox_cmd_get_event_interrupt_policy() *GET_EVENT_INTERRUPT_POLICY_OUTPUT

+ func (mb *CXLMailbox) Mailbox_cmd_get_event_records(event uint8) *get_event_records_output

+ func (mb *CXLMailbox) Mailbox_cmd_get_fw_info() *GET_FW_INFO_OUTPUT

+ func (mb *CXLMailbox) Mailbox_cmd_get_log(log_input [16]byte, offset uint32, length uint32) *get_log_output

+ func (mb *CXLMailbox) Mailbox_cmd_get_supported_logs() *get_supported_logs_output

+ func (mb *CXLMailbox) Mailbox_cmd_identify_memory_device() *IDENTIFY_MEMORY_DEVICE_OUTPUT

+ func (mb *CXLMailbox) Mailbox_cmd_set_event_interrupt_policy(setting []int) uint16

+ type ComponentRegistersPtr struct

+ HDM_Decoder_Cap *cmpreg_hdm_decoder_cap_struct

+ Link_Cap *CMPREG_LINK_CAP

+ Ras_Cap *CMPREG_RAS_CAP

type CxlDev

+ CmpReg *ComponentRegistersPtr

+ MailboxCCI *CXLMailbox

+ Memdev *MemoryDeviceRegisters

+ SerialNumber string

+ func (c *CxlDev) GetMemDevRegStruct(i int) any

+ func (c *CxlDev) GetSerialNumber() string

type CxlRev

+ const CXL_INVALID

+ type DEVICE_CAPABILITIES_ARRAY_REGISTER struct

+ Capabilities_Count uint16

+ Capability_ID uint16

+ Reserved uint8

+ Reserved2 [10]uint8

+ Version uint8

+ type DEVICE_CAPABILITIES_HEADER struct

+ Capability_ID uint16

+ Length uint32

+ Offset uint32

+ Reserved uint8

+ Reserved2 uint32

+ Version uint8

+ type HDM_DECODER struct

+ Base_High uint32

+ Base_Low uint32

+ Control uint32

+ DPA_Skip_High uint32

+ DPA_Skip_Low uint32

+ Reserved uint32

+ Size_High uint32

+ Size_Low uint32

+ type HDM_DECODER_CAP struct

+ A11to8_Interleave_Capable bitfield_1b

+ A14to12_Interleave_Capable bitfield_1b

+ Decoder_Cnt bitfield_4b

+ Interleave_Capable_16_Way bitfield_1b

+ Interleave_Capable_3_6_12_Way_ bitfield_1b

+ MemData_NXM_Capable bitfield_1b

+ Poison_On_Decode_Error_Capability bitfield_1b

+ Reserved bitfield_2b

+ Reserved2 bitfield_11b

+ Target_Cnt bitfield_4b

+ UIO_Capable bitfield_1b

+ UIO_Capable_Decoder_Count bitfield_4b

+ type HDM_DECODER_GLOBAL_CONTROL struct

+ HDMM_Decoder_En bitfield_1b

+ Poison_On_Decod_Err_En bitfield_1b

+ Reserved bitfield_30b

+ type MEMDEV_DEVICE_STATUS struct

+ Event_Status uint32

+ Reserved uint32

+ type MEMDEV_MEMDEV_STATUS struct

+ Device_Fatal bitfield_1b

+ FW_Halt bitfield_1b

+ Mailbox_Interfaces_Ready bitfield_1b

+ Media_Status bitfield_2b

+ Reserved bitfield_24b

+ Reserved2 uint32

+ Reset_Needed bitfield_3b

+ type MemoryDeviceRegisters struct

+ Device_Capabilities_Array_Register DEVICE_CAPABILITIES_ARRAY_REGISTER

+ Device_Capability []byte

+ Device_Capability_Header []DEVICE_CAPABILITIES_HEADER

+ func (m *MemoryDeviceRegisters) GetCapabilityByteArray(i int) []byte

+ type PCIE_DEVICE_SERIAL_NUMBER_CAP struct

+ Cap_Ver bitfield_4b

+ Next_Cap_ofs bitfield_12b

+ PCIE_ext_cap_ID bitfield_16b

+ SN_high uint32

+ SN_low uint32

v1.1.0

Jun 21, 2023

Changes in this version

+ var PciVendor map[string]string

v1.0.0

May 3, 2023

Changes in this version

+ const CXL_DVSEC_CXL2_0_EXR_DVESC

+ const CXL_DVSEC_GPF_DVSEC_FOR_DEV

+ const CXL_DVSEC_GPF_DVSEC_FOR_PORTS

+ const CXL_DVSEC_MLD

+ const CXL_DVSEC_NON_CXL_FUNC_MAP

+ const CXL_DVSEC_PCIE_DVSEC_FOR_CXL

+ const CXL_DVSEC_PCIE_DVSEC_FOR_FLEX_BUS_PORT

+ const CXL_DVSEC_PCIE_DVSEC_FOR_TEST_CAP

+ const CXL_DVSEC_REGISTER_LOCATOR

+ const CXL_DVSEC_UNDEFINED_ID1

+ const CXL_DVSEC_UNDEFINED_ID6

+ const CXL_Vendor_ID

+ const EXT_DVSEC_OFFSET

+ var ACPITables = ACPI

+ var CXL_FW_PACK_SIZE = 128

+ var MB_ReturnCode = [23]string

+ var PCI_MMCONFIG_BASE_ADDR int64

+ func BitFieldRead(r io.Reader, data any) error

+ func CEDT_TABLE(size uint) cedt_table_struct

+ func CLEAR_EVENT_RECORDS_INPUT(Record_Count uint) clear_event_records_output

+ func GET_EVENT_RECORDS_OUTPUT(Record_Count uint) get_event_records_output

+ func GET_LOG_OUTPUT(Length uint) get_log_output

+ func GET_SUPPORTED_LOGS_OUTPUT(Entries uint) get_supported_logs_output

+ func InitCxlDevList() map[string]*CxlDev

+ func MAILBOX_REGISTERS_CLASS(Length uint) mailbox_registers

+ func REGISTER_LOCATOR(Size uint) registerLocator

+ func ReadByBit(r io.Reader, buf []byte, m []int)

+ func TRASFER_FW_INPUT(transfer_size uint) trasfer_fw_input

+ func UintToBool(i bitfield_1b) bool

+ type ACPI struct

+ CEDT *cedt_table_struct

+ func (a *ACPI) FetchCedt()

+ func (a *ACPI) GetCedtCount() int

+ func (a *ACPI) GetCedtSubtable(i int) *CEDT_SUBTABLE

+ type ACPI_HEADER struct

+ Asl_Compiler_ID [4]byte

+ Asl_Compiler_Revision uint32

+ Checksum byte

+ Oem_ID [6]byte

+ Oem_Revision uint32

+ Oem_Table_ID [8]byte

+ Revision uint8

+ Signature [4]byte

+ Table_Length uint32

+ type BACKGROUND_COMMAND_STATUS_REGISTER struct

+ Command_Opcode bitfield_16b

+ Percentage_Complete bitfield_7b

+ Reserved bitfield_9b

+ Return_Code bitfield_16b

+ Vendor_Specific_Extended_Status bitfield_16b

+ type BAR struct

+ Base_Address bitfield_28b

+ Locatable bitfield_2b

+ Prefetchable bitfield_1b

+ Region_Type bitfield_1b

+ type BDF struct

+ Bus uint8

+ Device uint8

+ Domain uint16

+ Function uint8

+ type CEDT_SUBTABLE struct

+ Associated_host_bridge uint32

+ Length uint16

+ Register_base uint64

+ Register_length uint64

+ Reserved byte

+ Reserved2 uint32

+ Specification_version uint32

+ Subtable_Type byte

+ type COMMAND_REGISTER struct

+ Command_Opcode bitfield_16b

+ Payload_Length bitfield_21b

+ Reserved bitfield_27b

+ type CXL2_0_EXR_DVESC struct

+ Alt_Bus_Base uint8

+ Alt_Bus_Limit uint8

+ Alt_Mem_Base uint16

+ Alt_Mem_Limit uint16

+ Alt_Prefetch_Mem_Base uint16

+ Alt_Prefetch_Mem_Base_High uint32

+ Alt_Prefetch_Mem_Limit uint16

+ Alt_Prefetch_Mem_Limit_High uint32

+ CXL_Port_Ext_Stat CXL_PORT_EXT_STAT

+ CXL_RCRB_Base CXL_RCRB_BASE

+ CXL_RCRB_Base_High uint32

+ PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR

+ Port_Ctrl_Ext PORT_CTRL_EXT

+ type CXL_CAP struct

+ CXL_reset_Cap bitfield_1b

+ CXL_reset_mem_clr_cap bitfield_1b

+ CXL_reset_timeout bitfield_3b

+ Cache_Cap bitfield_1b

+ Cache_Writeback bitfield_1b

+ HDM_Count bitfield_2b

+ IO_Cap bitfield_1b

+ Mem_Cap bitfield_1b

+ Mem_HwInit_Mode bitfield_1b

+ Multiple_Logical_Device bitfield_1b

+ PM_Init_comp bitfield_1b

+ RsvdP bitfield_1b

+ Viral_Cap bitfield_1b

+ type CXL_CAP2 struct

+ Cache_Size bitfield_8b

+ Cache_Size_Unit bitfield_4b

+ RsvdP bitfield_4b

+ type CXL_CTRL struct

+ Cache_Clean_Eviction bitfield_1b

+ Cache_En bitfield_1b

+ Cache_SF_Coverage bitfield_5b

+ Cache_SF_Granularity bitfield_3b

+ IO_En bitfield_1b

+ Mem_En bitfield_1b

+ RsvdP bitfield_2b

+ RsvdP2 bitfield_1b

+ Viral_En bitfield_1b

+ type CXL_CTRL2 struct

+ CXL_Reset_Mem_Clr_En bitfield_1b

+ Disable_Caching bitfield_1b

+ Init_CXL_Rest bitfield_1b

+ Init_Cache_WriteBack bitfield_1b

+ RsvdP bitfield_12b

+ type CXL_DEVICE_CAPABILITIES_ARRAY_REGISTER struct

+ Capabilities_Count uint16

+ Capability_ID uint16

+ Reserved uint8

+ Reserved2 [10]uint8

+ Version uint8

+ type CXL_DEVICE_CAPABILITIES_HEADER struct

+ Capability_ID uint16

+ Length uint32

+ Offset uint32

+ Reserved uint8

+ Reserved2 uint32

+ Version uint8

+ type CXL_LOCK struct

+ CONFIG_LOCK bitfield_1b

+ RsvdP bitfield_15b

+ type CXL_PORT_EXT_STAT struct

+ Port_Power_Mangement_Initialized bitfield_1b

+ RsvdP bitfield_13b

+ RsvdP2 bitfield_1b

+ Viral_Stat bitfield_1b

+ type CXL_RANGE_BASE_HIGH struct

+ Memory_Base_High uint32

+ type CXL_RANGE_BASE_LOW struct

+ Memory_Base_Low bitfield_4b

+ RsvdP bitfield_28b

+ type CXL_RANGE_SIZE_HIGH struct

+ Memory_Size_High uint32

+ type CXL_RANGE_SIZE_LOW struct

+ Desired_Interleave bitfield_5b

+ Media_Type bitfield_3b

+ Memory_Active bitfield_1b

+ Memory_Active_Timeout bitfield_3b

+ Memory_Class bitfield_3b

+ Memory_Size_low bitfield_4b

+ Memory_info_Valid bitfield_1b

+ RsvdP bitfield_12b

+ type CXL_RCRB_BASE struct

+ CXL_RCRB_Base_Addr_Low bitfield_19b

+ CXL_RCRB_En bitfield_1b

+ RsvdP bitfield_12b

+ type CXL_STAT struct

+ RsvdP bitfield_14b

+ RsvdP2 bitfield_1b

+ Viral_Stat bitfield_1b

+ type CXL_STAT2 struct

+ CXL_Reset_Error bitfield_1b

+ CXL_Rest_Complete bitfield_1b

+ Cache_Invalid bitfield_1b

+ PM_Init_Complete bitfield_1b

+ RsvdP bitfield_12b

+ type CxlCaps struct

+ Cache_Cap bool

+ Cache_En bool

+ IO_Cap bool

+ IO_En bool

+ Mem_Cap bool

+ Mem_En bool

+ type CxlDev struct

+ Bdf *BDF

+ CXLdevtype CxlDevType

+ CXLrev CxlRev

+ PCIE []byte

+ Vendor string

+ func (c *CxlDev) GetBdfString() string

+ func (c *CxlDev) GetCedtField(field string) interface{}

+ func (c *CxlDev) GetCxlCap() CxlCaps

+ func (c *CxlDev) GetCxlRev() CxlRev

+ func (c *CxlDev) GetCxlType() CxlDevType

+ func (c *CxlDev) GetDeviceInfo() string

+ func (c *CxlDev) GetDvsec(dvsecId cxl_dvsec_id) interface{}

+ func (c *CxlDev) GetDvsecList() map[cxl_dvsec_id]uint32

+ func (c *CxlDev) GetMemoryBaseAddr() int64

+ func (c *CxlDev) GetMemorySize() int64

+ func (c *CxlDev) GetPcieHdr() *PCIE_CONFIG_HDR

+ func (c *CxlDev) GetVendorInfo() string

+ type CxlDevType string

+ const CXL_TYPE1_DEV

+ const CXL_TYPE2_DEV

+ const CXL_TYPE3_DEV

+ const CXL_UNKOWN_DEV

+ type CxlMemAttr struct

+ ReadBandwidth uint16

+ ReadLatency uint16

+ WriteBandwidth uint16

+ WriteLatency uint16

+ type CxlMemoryDeviceRegisters struct

+ CXL_Device_Capabilities_Array_Register CXL_DEVICE_CAPABILITIES_ARRAY_REGISTER

+ CXL_Device_Capability_Header []CXL_DEVICE_CAPABILITIES_HEADER

+ func CXL_MEMORY_DEVICE_REGISTERS(Size uint) CxlMemoryDeviceRegisters

+ type CxlRev string

+ const CXL_REV_1_1

+ const CXL_REV_2_0

+ const CXL_REV_3_0

+ const CXL_REV_UNKOWN

+ type DVSEC_FLEX_BUS_PORT_CAP struct

+ CXL2p0_Cap bitfield_1b

+ CXL_Multi_logic_cap bitfield_1b

+ Cache_Cap bitfield_1b

+ IO_Cap bitfield_1b

+ Mem_Cap bitfield_1b

+ RsvdP bitfield_2b

+ RsvdP2 bitfield_9b

+ type DVSEC_FLEX_BUS_PORT_CTRL struct

+ CXL2p0_En bitfield_1b

+ CXL_Multi_logic_En bitfield_1b

+ CXL_Sync_Hdr_Bypass_en bitfield_1b

+ Cache_En bitfield_1b

+ Disable_CXL1p1_Training bitfield_1b

+ Drift_buffer_En bitfield_1b

+ IO_En bitfield_1b

+ Mem_En bitfield_1b

+ Retimer1_Present bitfield_1b

+ Retimer2_Present bitfield_1b

+ RsvdP2 bitfield_6b

+ type DVSEC_FLEX_BUS_PORT_STAT struct

+ CXL2p0_En bitfield_1b

+ CXL_Cor_Protocol_ID_Fram_Err bitfield_1b

+ CXL_Multi_logic_En bitfield_1b

+ CXL_Sync_Hdr_Bypass_en bitfield_1b

+ CXL_UnExpct_Protocol_ID_Dropped bitfield_1b

+ CXL_unCor_Protocol_ID_Fram_Err bitfield_1b

+ Cache_En bitfield_1b

+ Drift_buffer_En bitfield_1b

+ FlexBusEnableBits_Phase2_Mismatch bitfield_1b

+ IO_En bitfield_1b

+ Mem_En bitfield_1b

+ Retimer_Present_Mismatched bitfield_1b

+ RsvdP bitfield_1b

+ RsvdP2 bitfield_3b

+ type DVSEC_FLEX_BUS_PORT_TS struct

+ Received_Flex_Bus_Data_Phase1 bitfield_24b

+ RsvdP bitfield_8b

+ type DVSEC_HDR1 struct

+ DVSEC_Length bitfield_12b

+ DVSEC_Rev bitfield_4b

+ DVSEC_Vendor_ID bitfield_16b

+ type DVSEC_HDR2 struct

+ DVSEC_ID uint16

+ type GET_EVENT_INTERRUPT_POLICY_OUTPUT struct

+ Failure_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS

+ Fatal_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS

+ Informational_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS

+ Warning_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS

+ type GET_FW_INFO_OUTPUT struct

+ FW_Activation_Capabilities uint8

+ FW_Slot_Info uint8

+ FW_Slots_Supported uint8

+ Reserved [13]uint8

+ Slot_FW [4]SLOT_FW_REVISION

+ type GET_LOG_INPUT struct

+ Length uint32

+ Log_Identifier [16]byte

+ Offset uint32

+ type GPF_DVSEC_FOR_DEV struct

+ GPF_Phase2_Duration GPF_PHASE2_DURATION

+ GPF_Phase2_Power_in_mW uint32

+ PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR

+ type GPF_DVSEC_FOR_PORTS struct

+ GPF_Phase1_Ctrl GPF_PHASE_CTRL

+ GPF_Phase2_Ctrl GPF_PHASE_CTRL

+ PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR

+ RsvdP uint16

+ type GPF_PHASE2_DURATION struct

+ Device_GPF_Phase_2_Time_Scale bitfield_4b

+ Device_GPF_Phase_2_Time_base bitfield_4b

+ RsvdP bitfield_4b

+ RsvdP2 bitfield_4b

+ type GPF_PHASE_CTRL struct

+ Port_GPF_Phase_TO_Scale bitfield_4b

+ Port_GPF_Phase_TO_base bitfield_4b

+ RsvdP bitfield_4b

+ RsvdP2 bitfield_4b

+ type IDENTIFY_MEMORY_DEVICE_OUTPUT struct

+ FW_Revision [16]byte

+ Failure_Event_Log_Size uint16

+ Fatal_Event_Log_Size uint16

+ Informational_Event_Log_Size uint16

+ Inject_Poison_Limit uint16

+ LSA_Size uint32

+ Partition_Aliggnment uint64

+ Persistent_Only_Capacitgy uint64

+ Poison_Handling_Capabilities uint8

+ Poison_List_Maximum_Media_Error_Records [3]uint8

+ Qos_Telemetry_Capabilities uint8

+ Total_Capaciity uint64

+ Volatile_Only_Capacity uint64

+ Warning_Event_Log_Size uint16

+ type INTERRUPT_SETTINGS struct

+ Interrupt_Message_Number bitfield_4b

+ Interrupt_Mode bitfield_2b

+ Reserved bitfield_2b

+ type MAILBOX_CAPABILITIES_REGISTER struct

+ Background_Command_Complete_Interrupt_Capable bitfield_1b

+ Interrupt_Message_Number bitfield_4b

+ MB_Doorbell_Interrupt_Capable bitfield_1b

+ Payload_Size bitfield_5b

+ Reserved bitfield_21b

+ type MAILBOX_CONTROL_REGISTER struct

+ Background_Command_Complete_Interrupt bitfield_1b

+ Doorbell bitfield_1b

+ MB_Doorbell_Interrupt bitfield_1b

+ Reserved bitfield_29b

+ type MAILBOX_STATUS_REGISTER struct

+ Background_Operation bitfield_1b

+ Reserved bitfield_31b

+ Return_Code bitfield_16b

+ Vendor_Specific_Extended_Status bitfield_16b

+ type MLD struct

+ LD_ID_Hot_Reset_Vector uint16

+ Num_LDs_Supported uint16

+ PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR

+ RsvdP uint16

+ type NON_CXL_FUNC_MAP struct

+ Non_CXL_Fun_Map_Reg [8]uint32

+ PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR

+ RsvdP uint16

+ type PCIE_CLASS_CODE struct

+ Base_Class_Code uint8

+ Prog_if uint8

+ Sub_Class_Code uint8

+ type PCIE_CONFIG_HDR struct

+ Base_Address_Registers [6]BAR

+ Class_Code PCIE_CLASS_CODE

+ Command uint16

+ Device_ID uint16

+ Misc uint32

+ Misc2 [6]int32

+ Rev_ID uint8

+ Status int16

+ Vendor_ID uint16

+ type PCIE_DVSEC_FOR_CXL struct

+ CXL_cap CXL_CAP

+ CXL_cap2 CXL_CAP2

+ CXL_ctrl CXL_CTRL

+ CXL_ctrl2 CXL_CTRL2

+ CXL_lock CXL_LOCK

+ CXL_range1_base_high CXL_RANGE_BASE_HIGH

+ CXL_range1_base_low CXL_RANGE_BASE_LOW

+ CXL_range1_size_high CXL_RANGE_SIZE_HIGH

+ CXL_range1_size_low CXL_RANGE_SIZE_LOW

+ CXL_range2_base_high CXL_RANGE_BASE_HIGH

+ CXL_range2_base_low CXL_RANGE_BASE_LOW

+ CXL_range2_size_high CXL_RANGE_SIZE_HIGH

+ CXL_range2_size_low CXL_RANGE_SIZE_LOW

+ CXL_stat CXL_STAT

+ CXL_stat2 CXL_STAT2

+ PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR

+ type PCIE_DVSEC_FOR_FLEX_BUS_PORT struct

+ DVSEC_flex_bus_port_Status DVSEC_FLEX_BUS_PORT_STAT

+ DVSEC_flex_bus_port_cap DVSEC_FLEX_BUS_PORT_CAP

+ DVSEC_flex_bus_port_control DVSEC_FLEX_BUS_PORT_CTRL

+ DVSEC_flex_bus_received_mod_TS_data_phase1 DVSEC_FLEX_BUS_PORT_TS

+ PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR

+ type PCIE_DVSEC_FOR_TEST_CAP struct

+ PCIE_ext_cap_hdr PCIE_EXT_CAP_HDR

+ type PCIE_EXT_CAP_HDR struct

+ Cap_Ver bitfield_4b

+ DVSEC_hdr1 DVSEC_HDR1

+ DVSEC_hdr2 DVSEC_HDR2

+ Next_Cap_ofs bitfield_12b

+ PCIE_ext_cap_ID bitfield_16b

+ type PORT_CTRL_EXT struct

+ Alt_BME bitfield_1b

+ Alt_Mem_and_ID_Space_En bitfield_1b

+ RsvdP bitfield_10b

+ RsvdP2 bitfield_1b

+ Unmask_Link_Disable bitfield_1b

+ Unmask_SBR bitfield_1b

+ Viral_En bitfield_1b

+ type REGISTER_BLOCK struct

+ Register_Offset_High REGISTER_OFFSET_HIGH

+ Register_Offset_Low REGISTER_OFFSET_LOW

+ type REGISTER_OFFSET_HIGH struct

+ Register_Block_Offset_High uint32

+ type REGISTER_OFFSET_LOW struct

+ Register_BIR bitfield_3b

+ Register_Block_Identifier bitfield_8b

+ Register_Block_Offset_Low bitfield_16b

+ RsvdP bitfield_5b

+ type SET_EVENT_INTERRUPT_POLICY_INPUT struct

+ Failure_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS

+ Fatal_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS

+ Informational_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS

+ Warning_Event_Log_Interrupt_Settings INTERRUPT_SETTINGS

+ type SLOT_FW_REVISION struct

+ FW_Revision [16]byte

+ type SUPPORTED_LOG_ENTRY struct

+ Log_Identifier [16]byte

+ Log_Size uint32

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