emu

package

v0.0.0-...-dfe74e1 Latest Latest Go to latest Published: Jan 28, 2024 License: MIT Imports: 1 Imported by: 0

Details

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Repository

github.com/aniou/morfe

Links

Open Source Insights

Documentation ¶

Constants ¶

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const (
	F_NONE = iota
	F_MAIN
)

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const (
	CPU_65c816 = 0
	CPU_68000  = 1
	CPU_68030  = 2
)

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const (
	M_USER = 0 // user mode
	M_SV   = 1 // supervisor mode
)

CPU modes - at this moment only for Motorola

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const (
	SYS_FOENIX_U = iota
	SYS_FOENIX_U_PLUS
	SYS_FOENIX_FMX
	SYS_FOENIX_A2560K
	SYS_FOENIX_GENX
)

a different platforms with different layouts of memory map and registers

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const (
	R0_FNX0_INT00_SOF   = 1    // Start of Frame @ 60FPS
	R0_FNX0_INT01_SOL   = 2    // Start of Line (Programmable)
	R0_FNX0_INT02_TMR0  = 4    // Timer 0 Interrupt
	R0_FNX0_INT03_TMR1  = 8    // Timer 1 Interrupt
	R0_FNX0_INT04_TMR2  = 0x10 // Timer 2 Interrupt
	R0_FNX0_INT05_RTC   = 0x20 // Real-Time Clock Interrupt
	R0_FNX0_INT06_FDC   = 0x40 // Floppy Disk Controller
	R0_FNX0_INT07_MOUSE = 0x80 // Mouse Interrupt (INT12 in SuperIO IOspace)
)

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const (
	R1_FNX1_INT00_KBD    = 1    // Keyboard Interrupt
	R1_FNX1_INT01_SC0    = 2    // Sprite 2 Sprite Collision
	R1_FNX1_INT02_SC1    = 4    // Sprite 2 Tiles Collision
	R1_FNX1_INT03_COM2   = 8    // Serial Port 2
	R1_FNX1_INT04_COM1   = 0x10 // Serial Port 1
	R1_FNX1_INT05_MPU401 = 0x20 // Midi Controller Interrupt
	R1_FNX1_INT06_LPT    = 0x40 // Parallel Port
	R1_FNX1_INT07_SDCARD = 0x80 // SD Card Controller Interrupt
)

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const (
	R2_FNX2_INT00_OPL2R   = 1    // OPL2 Right Channel
	R2_FNX2_INT01_OPL2L   = 2    // OPL2 Left Channel
	R2_FNX2_INT02_BTX_INT = 4    // Beatrix Interrupt (TBD)
	R2_FNX2_INT03_SDMA    = 8    // System DMA
	R2_FNX2_INT04_VDMA    = 0x10 // Video DMA
	R2_FNX2_INT05_DACHP   = 0x20 // DAC Hot Plug
	R2_FNX2_INT06_EXT     = 0x40 // External Expansion
	R2_FNX2_INT07_ALLONE  = 0x80 // ??
)

View Source

const (
	R2FMX_FNX2_INT00_OPL3       = 1    // OPL3
	R2FMX_FNX2_INT01_GABE_INT0  = 2    // GABE (INT0) - TBD
	R2FMX_FNX2_INT02_GABE_INT1  = 4    // GABE (INT1) - TBD
	R2FMX_FNX2_INT03_SDMA       = 8    // VICKY_II (INT4)
	R2FMX_FNX2_INT04_VDMA       = 0x10 // VICKY_II (INT5)
	R2FMX_FNX2_INT05_GABE_INT2  = 0x20 // GABE (INT2) - TBD
	R2FMX_FNX2_INT06_EXT        = 0x40 // External Expansion
	R2FMX_FNX2_INT07_SDCARD_INS = 0x80 // SDCARD Insertion
)

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const (
	R3FMX_FNX3_INT00_OPN2 = 1    // OPN2
	R3FMX_FNX3_INT01_OPM  = 2    // OPM
	R3FMX_FNX3_INT02_IDE  = 4    // HDD IDE INTERRUPT
	R3FMX_FNX3_INT03_TBD  = 8    // TBD
	R3FMX_FNX3_INT04_TBD  = 0x10 // TBD
	R3FMX_FNX3_INT05_TBD  = 0x20 // GABE (INT2) - TBD
	R3FMX_FNX3_INT06_TBD  = 0x40 // External Expansion
	R3FMX_FNX3_INT07_TBD  = 0x80 // SDCARD Insertion
)

Variables ¶

View Source

var (
	DIP = [9]bool{false} // there are 8 switches, but numbering from 1 is convinient

)

Functions ¶

This section is empty.

Types ¶

type Bus ¶

type Bus interface {
	Write_8(byte, uint32, byte)
	Read_8(byte, uint32) byte
}

type GPU ¶

type GPU interface {
	Write(fn byte, addr uint32, value byte) error
	Read(fn byte, addr uint32) (byte, error)
	Name(fn byte) string
	Size(fn byte) (uint32, uint32)

	GetCommon() *GPU_common
	RenderBitmapText()
}

type GPU_common ¶

type GPU_common struct {
	TFB   []uint32 // text   framebuffer
	BM0FB []uint32 // bitmap0 framebuffer
	BM1FB []uint32 // bitmap1 framebuffer

	// 'new' identifiers
	Text_enabled    bool
	Graphic_enabled bool
	Bitmap_enabled  bool
	Border_enabled  bool

	Border_color_b byte
	Border_color_g byte
	Border_color_r byte
	Border_x_size  int32
	Border_y_size  int32

	Screen_resized bool
	Screen_x_size  int32
	Screen_y_size  int32

	Cursor_rate    int32
	Cursor_visible bool // set by timer in main GUI, for blinking

	// some convinient registers that should be converted
	// into some kind of memory indexes...
	// Master_L        byte    // MASTER_CTRL_REG_L
	// Master_H        byte    // MASTER_CTRL_REG_H
	BM0_visible bool
	BM1_visible bool

	Background [3]byte // r, g, b
}

a 'common' set of Vicky's data

type Memory ¶

type Memory interface {
	Write(fn byte, addr uint32, value byte) error
	Read(fn byte, addr uint32) (byte, error)
	Name(fn byte) string
	Size(fn byte) (uint32, uint32)
}

type Processor ¶

type Processor interface {
	Reset()
	Execute() uint32                 // execute one or more steps and returns used cycles
	Step() uint32                    // execute single step and returns used cycles
	GetRegisters() map[string]uint32 // returns all registers of CPU
	GetType() uint                   // returns CPU id (when many types are available)
	IsEnabled() bool                 // as name suggests
	Enable(bool)                     // enables/disables CPU
	Dissasm() string
	GetCycles() uint32    // number of cycles used by last step
	GetAllCycles() uint64 // cumulative number of cycles used
	StatusString() string // string that represents status flags
	ResetCycles()
	TriggerIRQ(byte)                  // irq number as parameter - may be ignored on some CPUs
	SetRegister(string, uint32) error // set selected register
	SetPC(uint32)                     // redundant to SetRegister but convinient

	Write_8(uint32, byte) // write byte to   cpu memory
	Read_8(uint32) byte   // read  byte from cpu memory

	GetName() string              // get id as "cpu0" / "cpu1" of unit
	DisassembleCurrentPC() string // disassemble current line
}

Source Files ¶

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