Documentation ¶
Overview ¶
Package sysinfo provides host detection information.
It is intended to be complimentary to github.com/klauspost/cpuid and golang.org/x/sys/cpu.
Index ¶
Constants ¶
This section is empty.
Variables ¶
This section is empty.
Functions ¶
This section is empty.
Types ¶
type CPU ¶
type CPU struct { // Proc is the processor number, usually zero-indexed. // // Matches: processor Proc int `json:"processor"` // BogoMIPS is a Linux-specific rough measurement of CPU // performance. // // Matches: BogoMIPS, bogomips BogoMIPS float64 `json:"bogomips,omitempty"` // Features is the set of supported CPU features or flags. // // Matches: Features, flags Features []string `json:"features,omitempty"` // Rev is the CPU "stepping" or revision. // // Matches: CPU revision, stepping Rev int `json:"revision,omitempty"` // ModelName is the human-readable CPU model name. // // Matches: model name ModelName string `json:"model_name,omitempty"` // MicroArch is the CPU's microarchitecture. MicroArch string `json:"micro_arch"` // Impl is the CPU implementer. // // Matches: CPU implementer Impl Implementer `json:"implementer,omitempty"` // Arch is the CPU architecture. // // Matches: CPU architecture Arch int `json:"arch,omitempty"` // Variant is the CPU variant. // // Matches: CPU variant Variant int `json:"variant,omitempty"` // Part identifies the specific CPU. // // Matches: CPU part Part Part `json:"part_number,omitempty"` // VendorID identifies the CPU vendor. // // Typically is "GenuineIntel" for Intel CPUs and // "AuthenticAMD" for AMD CPUs. // // Matches: vendor_id VendorID string `json:"vendor_id,omitempty"` // Family is the CPU family. // // Matches: cpu family Family int `json:"family,omitempty"` // Model is the CPU model number. // // Matches: model Model int `json:"model_number,omitempty"` // Microcode is the CPU's microcode version. // // Matches: microcode Microcode int `json:"microcode_version,omitempty"` // Freq is the CPU frequency in MHz. // // Matches: cpu MHz Freq float64 `json:"frequency_mhz,omitempty"` // Cache is the CPU's cache information. Cache Cache `json:"cache,omitempty"` // PhysID is the physical ID of this CPU core. // // Matches: physical id PhysID int `json:"physical_id,omitempty"` // Siblings is the number of sibling CPUs. // // Matches: siblings Siblings int `json:"siblings,omitempty"` // CoreID is the unique ID of this CPU core. // // Matches: core id CoreID int `json:"core_id,omitempty"` // Cores is the number of CPU cores. // // Matches: cores Cores int `json:"num_cores,omitempty"` // APICID is the APIC system's unique ID. // // Matches: apicid APICID int `json:"apic_id,omitempty"` // InitAPICID is the APIC system's unique ID as assigned at // startup. // // Matches: initial apicid InitAPICID int `json:"initial_apic_id,omitempty"` // FPU is whether the CPU has floating-point unit. // // Matches: fpu FPU bool `json:"fpu,omitempty"` // FPUExceptions is whether the CPU supports floating-point // unit exceptions. // // Matches: fpu_exceptions FPUExceptions bool `json:"fpu_exceptions,omitempty"` // CPUID level is the maximum CPUID level that can be used // when querying the CPU for information via the CPUID // instruction. // // Matches: cpuid level CPUIDLevel int `json:"cpuid_level,omitempty"` // WP is whether the CPU supports write protection. // // Matches: wp WP bool `json:"write_protection,omitempty"` // Bugs the set of bugs that have been detected or worked // around. // // Matches: bugs Bugs []string `json:"bugs,omitempty"` // AddrSizes are the CPU's memory address sizes. // // Matches: address sizes AddrSizes struct { // Phys is the number of bits in a physical memory // address. Phys int `json:"physical_bits,omitempty"` // Virt is the number of bits in a virtual memory // address. Virt int `json:"virtual_bits,omitempty"` } `json:"address_sizes,omitempty"` // PowerMgmt is the supported power management features. // // Matches: power management. PowerMgmt string `json:"power_management,omitempty"` // TLB is the CPU's Translation Lookaside Buffer. // // Matches: TLB size TLB struct { // N is the number of TLB pages. N int `json:"num_pages,omitempty"` // PageSize is the size in bytes of each page. PageSize int `json:"page_size,omitempty"` } `json:"tlb,omitempty"` }
CPU describes a single CPU.
On Linux, this information is read from /proc/cpuinfo. On BSDs (including macOS), this information is read from sysctl.
Each read from /proc/cpuinfo has a "Matches:" comment describing the key used.
type Cache ¶
type Cache struct { // Inst is the size in bytes of the CPU's instruction // cache. Inst int `json:"instruction,omitempty"` // L1Data is the size in bytes of the CPU's L1 data // cache. L1 int `json:"l1,omitempty"` // L2 is the size in bytes of the CPU's L2 cache. // // Matches: cache size L2 int `json:"l2,omitempty"` // L3 is the size in bytes of the CPU's L3 cache. L3 int `json:"l3,omitempty"` // Alignment is how the CPU caches are aligned. // // Matches: cache_alignment Alignment int `json:"alignment,omitempty"` // Flush is the size of a cache line flush (CLFLUSH). // // Matches: clflush size Flush int `json:"flush,omitempty"` }
type Implementer ¶
type Implementer uint8
const ( ARMLtd Implementer = 'A' // ARM Ltd Broadcom Implementer = 'B' // Broadcom Cavium Implementer = 'C' // Cavium Fujitsu Implementer = 'F' // Fujitsu Ltd NVIDIA Implementer = 'N' // NVIDIA Corporation HiSilicon Implementer = 'H' // HiSilicon Technologies Inc Qualcomm Implementer = 'Q' // Qualcomm Technologies Inc Samsung Implementer = 'S' // Samsung Technologies Inc Intel Implementer = 'i' // Intel ARM parts Apple Implementer = 'a' // Apple Inc )
func (Implementer) MarshalText ¶
func (i Implementer) MarshalText() ([]byte, error)
func (Implementer) String ¶
func (i Implementer) String() string
type Info ¶
type Pair ¶
type Pair struct {
Key, Value string
}
Pair is a miscellaneous piece of data reported by the host.
type Part ¶
type Part uint16
const ( ARM926EJS Part = 0x926 // ARM926EJ-S ARM11MPCore Part = 0xb02 // ARM11-MPCore ARM1136JS Part = 0xb36 // ARM1136J-S ARM1156T2S Part = 0xb56 // ARM1156T2-S ARM1176JZS Part = 0xb76 // ARM1176JZ-S CortexA8 Part = 0xc08 // Cortex-A8 CortexA9 Part = 0xc09 // Cortex-A9 CortexA15 Part = 0xc0f // Cortex-A15 CortexM0 Part = 0xc20 // Cortex-M0 CortexM3 Part = 0xc23 // Cortex-M3 CortexM4 Part = 0xc24 // Cortex-M4 CortexM55 Part = 0xd22 // Cortex-M55 CortexA34 Part = 0xd02 // Cortex-A34 CortexA35 Part = 0xd04 // Cortex-A35 CortexA53 Part = 0xd03 // Cortex-A53 CortexA55 Part = 0xd05 // Cortex-A55 CortexA57 Part = 0xd07 // Cortex-A57 CortexA72 Part = 0xd08 // Cortex-A72 CortexA73 Part = 0xd09 // Cortex-A73 CortexA75 Part = 0xd0a // Cortex-A75 CortexA76 Part = 0xd0b // Cortex-A76 CortexA77 Part = 0xd0d // Cortex-A77 CortexA78 Part = 0xd41 // Cortex-A78 CortexX1 Part = 0xd44 // Cortex-X1 CortexX1C Part = 0xd4c // Cortex-X1C NeoverseN1 Part = 0xd0c // neoverse N1 NeoverseN2 Part = 0xd49 // Neoverse N2 NeoverseV1 Part = 0xd40 // Neoverse V1 Firestorm Part = 0x23 // M1 Firestorm Icestorm Part = 0x22 // M1 Icestorm )
ARM
const ( ThunderX2T99 Part = 0x516 // thunderx2t99 ThunderX2T99_2 Part = 0xaf // thunderx2t99 ThunderXT88 Part = 0xa1 // thunderxt88 )
Broadcom/Cavium
const ( Krait Part = 0x06f // krait Kryo Part = 0x201 // kryo Kryo_2 Part = 0x205 // kryo Kryo_3 Part = 0x211 // kryo Kryo2xxGold Part = 0x800 // cortex-a73 Kryo2xxSilver Part = 0x801 // cortex-a73 Kryo3xxGold Part = 0x802 // cortex-a75 Kryo3xxSilver Part = 0x803 // cortex-a75 Kryo4xxGold Part = 0x804 // cortex-a76 Kryo4xxSilver Part = 0x805 // cortex-a76 Falkor Part = 0xc00 // falkor Saphira Part = 0xc01 // saphira )
const (
A64FX Part = 0x001 // a64fx
)
Fujitsu
const (
Carmel Part = 0x004 // carmel
)
NVIDIA
const (
TSV110 Part = 0xd01 // tsv110
)
HiSilicon
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